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ADV7195
PIN FUNCTION DESCRIPTIONS
Pin
1, 12
2–11
Mnemonic
V DD
Y0–Y9
Input/Output
P
I
Function
Digital Power Supply
10-Bit Progressive Scan/HDTV Input Port for Y Data. Input for G data when
RGB data is input.
13, 52
14–23
GND
Cr0–Cr9
G
I
Digital Ground
1 0-Bit Progressive Scan/HDTV Input Port for Color Data in 4:4:4 Input Mode.
In 4:2:2 mode this input port is not used. Input port for R data when RGB
data is input.
24, 35
25
V AA
CLKIN
P
I
Analog Power Supply
Pixel Clock Input. Requires a 27 MHz reference clock for standard operation in
Progressive Scan Mode or a 74.25 MHz (74.1758 MHz) reference clock in
HDTV mode.
26, 33
27
28
29
30
31
32
34
36
37
38
AGND
DV
VSYNC/
TSYNC
HSYNC/
SYNC
SCL
SDA
DAC C
DAC A
DAC B
COMP
R SET
G
I
I
I
I
I/O
O
O
O
O
I
Analog Ground
Video Blanking Control Signal Input
VSYNC , Vertical Sync Control Signal Input or TSYNC Input Control Signal in
Async Timing Mode
HSYNC , Horizontal Sync Control Signal Input or SYNC Input Control Signal in
Async Timing Mode
MPU Port Serial Interface Clock Input
MPU Port Serial Data Input/Output
Color Component Analog Output of Input Data on Cb/Cr9–0 Input Pins
Y Analog Output
Color Component Analog Output of Input Data on Cr9–Cr0 Input Pins
Compensation Pin for DACs. Connect 0.1 μ F Capacitor from COMP pin to V AA .
A 2470 ? resistor for input ranges 64–940 and 64–960 (output standards EIA-
770.1–EIA-770.3) must be connected from this pin to ground and is used to
control the amplitudes of the DAC outputs. For input ranges 0–1023 (output
standards RS-170, RS-343A) the R SET value must be 2820 ? .
39
V REF
I/O
Optional External Voltage Reference Input for DACs or Voltage Reference Out-
put (1.235 V)
40
RESET
I
This input resets the on-chip timing generator and sets the ADV7195 into Default
Register setting. Reset is an active low signal.
41
ALSB
I
TTL Address Input. This signal sets up the LSB of the MPU address. When this
pin is tied high, the I 2 C filter is activated, which reduces noise on the I 2 C Interface.
When this pin is tied low, the input bandwidth on the I 2 C interface is increased.
42–51
Cb/Cr9–0
I
1 0-Bit Progressive scan/HDTV input port for color data. In 4:2:2 mode the
multiplexed CrCb data must be input on these pins. Input port for B data when
RGB is input.
REV. A
–9 –
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